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-
- *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*
- MC68040 ToolKit - programming details
- *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*
-
- Direct access to the MMU tree is implemented via the 'XMMU' cookie. This
- cookie is filled out with a longword pointer to a short structure which
- contains useful addresses & routines for use by external programs. All
- the routines listed here should be called from supervisor mode. Avoid
- modifying pages assigned to locations used by the current ISP/USP.
-
- The XMMU cookie structure uses the following format:
-
- Offset: Name/purpose:
-
- 0 PMMU root table pointer (512-byte aligned). This address
- should also be contained in the URP & SRP root-pointer
- registers after the driver is installed.
-
- 4 PMMU tree end address. This address points to the first
- memory location NOT used by the PMMU tree.
-
- 8 Read pages. This is a pointer to a subroutine which can
- be used to 'record' the page attributes of a block of
- memory between registers 'a0' and 'a1'. Page attributes
- are recorded into a buffer indicated by register 'a2'.
- One longword is stored in the buffer for every 8-KByte
- page overlapping the address range indicated by registers
- 'a0' and 'a1'. The block end address - 'a1' - is assumed
- to point to the first location NOT included in the block.
- Because these pages are 8kb in size, this routine will
- record attributes for any page overlapping the block
- specified - even if the page is not contained entirely
- within that block.
-
- 12 Write pages. Identical to 'read pages', but in reverse.
- This must be used to restore page attributes when your
- program terminates. Again, a0/a1/a2 are used to indicate
- block start, end and the attribute buffer respectively.
-
- 16 Set pages to 'write-through' cache mode. Similar to
- 'write pages', except the only thing that changes in
- the page attributes is the cache mode - and a source
- buffer is not required. This can be used to ensure an
- area of memory is cacheable, but is not using copyback
- mode.
-
- 20 Set pages to 'copyback' cache mode. Identical to the
- 'write-through' version described above, except the
- cache mode is different. Can be used to accelerate all
- access to BSS storage segments and program stack space.
-
- 24 Set pages to 'serialized' cache mode. This mode means
- the memory is not cacheable, but the data is written
- to ram in the same order specified by the instruction
- sequence. This is important if you are marking new
- hardware registers not present in the usual Falcon HW
- register space - like the Nova card.
-
- 28 Set pages to 'non-serialized' cache mode. Identical to
- the 'serialized' mode described above, except this time
- the data can be written back to ram out-of-order to
- take advantage of long-latency operations & optimised
- 68040 bus situations.
-
-
- Notes: The idea is this: Record the page attributes of the
- memory you want to edit using 'read pages'. Change the
- page attributes using the copyback routine (or whatever)
- and then use 'write-pages' to put the attributes back
- when you have finished.
-
-